1. Field of the Invention
The present invention concerns an EPROM-type integrated device with metallic source connections and a process for the manufacture of EPROM cells of markedly reduced dimensions as compared to the minimum dimensions that can be obtained with conventional photolithographic definition techniques, by employing metallic source connections.
2. Description of the Prior Art
EPROM devices or memories are well known and widely used in modern digital technologies. These integrated semiconductor devices are characterized in that they have one or more arrays of EPROM memory unit cells, individually addressed and organized in rows and columns, each of which essentially comprises a floating-gate (or double-gate) MOS transistor. The conventional architecture of these arrays of EPROM cells is also known, characterized by the presence of interconnection lines of drain contacts, belonging to transistors (cells) of the same column, perpendicular to gate lines. The sources of two cells (floating-gate MOS transistors) which are adjacent to each other in the direction of column alignment of the cells are electrically connected in common and, in a conventional array architecture, cells belonging to the same row have their sources electrically connected in common. In these devices the field isolation structures which separate the drains and gates of pairs of transistors arranged in the same row have an essentially rectangular geometry (see FIG. 10), whether they are embedded (e.g. of the BOX type) or formed by thermally growing a thick layer of field oxide. Usually drain contacts are formed by purposely masking and etching a dielectric layer uniformly deposited on the surface of the semiconductor wafer to insulate the transistor gate lines or structures.
As regards the possibility of photolithographic definition of ever smaller features, the above mentioned topographic aspects of the "traditional" architecture of these devices present the following problems.